Focal Plane Architecture with On-Chip ADC and Compression for High- Resolution, High-Speed Digital Video Capture
نویسندگان
چکیده
We present a new CMOS readout architecture that provides near lossless in-stream compression of 10-bit video data at rates up to 1000 frames per second on large focal plane arrays. The correctness of the circuit design in performing all logic operations at data rates of interest has been fully tested and verified in fabricated prototype arrays. The architecture can be combined with different sensing materials through 3-D integration to permit imaging in different spectral regions.
منابع مشابه
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the rat...
متن کاملSpeed Optimization and Capacitor Mismatch Calibration for High-Resolution High-Speed Pipelined A/D Converters
System-on-a-chip (SOC) requires integration of analog circuits and digital circuits on a single silicon chip to decrease cost, power dissipation, volume and radiant noise from the data bus on the printed circuit board (PCB). For these mixed-signal intergrated circuits, the standard digital CMOS technology is the best choice in view of cost, power dissipation and implementation convenience. The ...
متن کاملOn-Focal-Plane Signal Processing for Current-Mode Active Pixel Sensors
On-focal-plane signal processing for current-mode active pixel sensors (APS), including fixed pattern noise (FPN) suppression and high-resolution analog-to-digital conversion (ADC), is presented. An FPN suppression circuit that removes the offset current variation between pixels by using a combination of an n-type and a p-type current copier cell is described. The FPN suppression circuit exhibi...
متن کاملDesign and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)
Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...
متن کاملVision systems based on the 128×128 focal plane cellular visual microprocessor chips
Focal Plane Cellular Visual Microprocessor chip development reached the necessary technology level that it can be applied in industrial vision systems. These TeraOPS speed, internally analog visual chips can capture and process thousands of medium resolution images in a second. The price for this extraordinary high speed is that their hardware-software environment and programming method is far ...
متن کامل